Job Details

Physical Design Engineer

Beaverton, Oregon, United States

Hardware

Summary

Posted: May 22, 2025

Weekly Hours: 40

Role Number: 200605058

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn’t have imagined, and now, can’t imagine living without. It’s the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Beaverton, Oregon. Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle. Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals. Perform timing, physical, and electrical verification, and drive the signoff closure for the partitions. Resolve design and flow issues related to the physical design, identify potential solutions, and drive execution. Perform Physical Design implementation of partitions and develop/test place and route flows. Implement physical design of partitions and top level. Develop and test place and route flows. Conduct floor planning, pin assignments, macro placement and evaluation of logic. Iterate over placement to get the optimized placement and timing. Perform clock tree synthesis, optimization, routing, and post-route optimization. Conduct setup, hold, transition, and other static timing checks and closure. Run Static Voltage Droop and dynamic Voltage Droop and other power related optimization and signoff. Conduct formal checking and signoff, full chip timing closure, physical verification and closure, and signoff checklist closure. 40 hours/week.

Minimum Qualifications

• Master’s degree or foreign equivalent in Electrical Engineering or related field

• Education and/or experience must include the following skills:

• Using digital circuit design concept to implement chip partitions

• Understanding semiconductor device physics to make a trade-off to achieve the best power and performance area in chip partition implementation.

• Understanding semiconductor layout design techniques to manually clean up design rule violations and write scripts.

• Utilizing knowledge of electrical circuit analysis to solve partition timing, IR drop, and electromagnetic issues.

• Using TCL and Python to develop place and route flow for designing chip partitions.

• Using Hardware Coding – Verilog as input to place and route tool and verify the implemented layout's correctness.

• Using Static Timing Analysis to verify the performance of the design implementation.

Preferred Qualifications

• N/A

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.Learn more about your EEO rights as an applicant (https://www.eeoc.gov/sites/default/files/2023-06/22-088_EEOC_KnowYourRights6.12ScreenRdr.pdf) .

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.Learn more about your EEO rights as an applicant (https://www.eeoc.gov/sites/default/files/2023-06/22-088_EEOC_KnowYourRights6.12ScreenRdr.pdf) .

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