Job Details

Role Number: 200641042-0157

Summary

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn’t have imagined, and now, can’t imagine living without. It’s the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Austin, Texas. Collaborate with design team to understand design specification and area requirement before starting the physical aspects including PnR. Understand the design data flow and pin placement and develop the feasible macro or hard Ip placement as needed. Conduct power grid planning to ensure a reliable and efficient power distribution at initial stage of design and understand the EM/IR violations and limits to avoid future challenges. Meet timing requirements by optimizing the design for critical paths and addressing setup and hold time violation. Understand the criticality and impact of timing constraints on design through discussions with the Static Timing Analysis (STA) team. Perform physical verification checks to ensure design adheres to design rules and guidelines. Address issues related to Design Rule checks (DRCs), layout vs schematic (LVS) and electrical rule checks (ERC) and bring up to PDV team if there are flow related issues. Understand the impact of the changing technology node on the design constraints and conducting multiple experiments to achieve PPA. Work closely with various teams to provide continuous feedback so that the design is easily able to close within the given timeframe and achieve the project milestone. 40 hours/week.

Minimum Qualifications

• Master's degree or foreign equivalent in Electrical Engineering, Electronics Engineering, or a related field and 3 years of experience in the job offered or related occupation.

• Experience and/or education must include:

• Using VLSI System Design, MOS VLSI Circuit Design, or Computer System with transistor level fundamentals and design architecture for all physical design work and troubleshooting.

• Using Innovus or IC Compiler for block level floor planning, place and route.

• Using Primetime for hierarchical design approach, top-down design, budgeting, timing closure.

• Using Caliber for physical verification for design rule closure.

• Using Voltus for electrical analysis.

• Using Genus or DC Compiler and Innovus or IC Compiler to work with RTL teams to drive optimal floor planning and physical implementation through early RTL feedback

• Using Innovus or IC Compiler for innovative physical construction and optimization flows to push performance, power, and Area (PPA)

• Using scripting languages including Perl/Tcl/Python for parsing physical design reports, logs and creating design metrics that capture the state of the design and to configure tool capabilities.

• Utilizing existing signoff process and flow to tapeout high quality product with no escape.

Preferred Qualifications

• N/A

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (https://www.eeoc.gov/sites/default/files/2023-06/22-088_EEOC_KnowYourRights6.12ScreenRdr.pdf) .