Job Details

Design Verification Engineer

Beaverton, Oregon, United States

Hardware

Summary

Posted: Jun 20, 2025

Weekly Hours: 40

Role Number: 200607931

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn’t have imagined, and now, can’t imagine living without. It’s the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Beaverton, Oregon. Collaborate with all disciplines (vertical product model), including design and micro-architecture. Ensure the quality of the SOC or an IP or subsystem. Review design and architecture specifications and work closely with design & micro-architecture teams. Understand the functional and performance goals of the design and use this knowledge to test effectively. Develop test plans, tests, and coverage plans and define Apple’s next-generation verification methodology and test benches. Communicate and collaborate with design, architecture and software to understand the use cases and corner conditions and drive test cases. Run and triage regressions, track bugs, and analyze coverage to achieve top results. Test bench development in Verilog. Perform programming in Python, Perl or similar scripting language. Test bench development using Universal Verification Methodology (UVM). 40 hours/week.

Minimum Qualifications

• Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering or related field and 2 years of experience in the job offered or related occupation.

• 6 months of experience in each of the following skills:

• Utilizing System Verilog and UVM framework to write test bench code

• Creating test plans to verify ASICs

• Utilizing C to write programs for ASIC/embedded tests

• Reviewing design and architecture specifications and working with design and micro-architecture teams to understand functional and performance goals

• Developing test coverage plan, collecting test bench coverage, and resolving coverage gaps in ASIC test suite

• Implementing IP block test environments and test cases for ASICs

• Utilizing Xcelium, Questa, or VCS to analyze simulation failures

• Experience in program scripts in Python or Perl to automate test bench analysis

Preferred Qualifications

• N/A

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.Learn more about your EEO rights as an applicant (https://www.eeoc.gov/sites/default/files/2023-06/22-088_EEOC_KnowYourRights6.12ScreenRdr.pdf) .

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.Learn more about your EEO rights as an applicant (https://www.eeoc.gov/sites/default/files/2023-06/22-088_EEOC_KnowYourRights6.12ScreenRdr.pdf) .

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