Job Details

Role Number: 200641038-0157

Summary

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn’t have imagined, and now, can’t imagine living without. It’s the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Austin, Texas. Run static timing analysis (STA) tools on design. Identify changes in the design that affect the timing of a chip. Create engineering change orders (ECOs) for fixing timing issues in the design. Work with the physical design team to highlight issues and best practices. Create and maintain scripts for runtime to ensure optimization and efficient analysis of the design to highlight timing flaws in design. Perform timing flow development to automate the STA flow so other teams can get results with a push button. Document and help to create guidelines and specifications for the timing of the product and integrate it at the top level. Work with the design team to understand and debug timing constraints to ensure accurate analysis of the design. 40 hours/week.

Minimum Qualifications

• Master’s degree or foreign equivalent in Electrical Engineering or related field and 3 years of experience in the job offered or related occupation.

• Experience and/or education must include:

• Using Verilog to parse register-transfer level (RTL) or netlists and identifying timing connectivity issues and timing issues.

• Using industry-standard Static timing analysis (STA) tools, including PrimeTime SI or Tempus, to analyze the timing of the design.

• Writing Synopsys design constraints (SDC) based STA timing constraints to create guidelines and specifications.

• Working with logic optimization in the data path for complex blocks using industry standard or custom tools to meet timing, performance and power targets.

• Working with RTL design teams and implementation teams to assess feasibility and impact of new features on power, area and timing metrics.

• Using industry standard or custom tools, ensure design convergence and signoff of complex blocks in advanced timing nodes.

Preferred Qualifications

• N/A

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (https://www.eeoc.gov/sites/default/files/2023-06/22-088_EEOC_KnowYourRights6.12ScreenRdr.pdf) .